High-speed analog-to-digital converters (ADCs) operate at extremely high sampling rates to generate digital samples. For example, an 8-bit, 10 GSa/sec ADC used in a high-speed conversion system generates digital samples at a data rate of 80 Gbit/sec. Conventional ADCs typically output digital samples at the rate at which the digital samples are generated, i.e., at a data rate of 80 Gbit/s in the above example. To output digital samples at such high data rates, conventional ADCs typically use either wide output busses, high-speed output busses or output busses that are both wide and high-speed to achieve the necessary data rate. ADCs with wide output busses require packages having a high pin count. This significantly increases the cost of the package and the complexity of designing a printed circuit to accommodate the package. ADCs with high-speed data busses require careful design to ensure the integrity of the data signals as the data signals pass from the ADC chip to the printed circuit board. This involves much care and effort in the design of the package and of the printed circuit board on which the package is mounted.
A typical approach to the design of a very high-speed data bus is to design the outputs of the integrated circuit (chip) in which the ADC is built to be as fast as possible. The maximum output speed attainable is influenced by such factors as the processing technology to be used to fabricate the chip and the availability of a custom package and special printed circuit board design. Once the maximum output speed has been determined, as many outputs are used as are necessary to obtain the required output data rate. This can lead to a design in which the chip has a large number of outputs and the package has a correspondingly large number of pins. This results in a large-area chip design housed in a large-area package that occupies a large area of the printed circuit board. The large number of maximum-speed outputs also increases the total power consumption and gives rise to the need to remove a corresponding large amount of heat from the package.
What is needed, therefore, is an analog-to-digital conversion system capable of sampling an analog input signal at a high sampling rate but that does not suffer from the shortcomings described above.
The invention provides an analog-to-digital conversion system that comprises an analog-to-digital converter that includes a digital output, memory having a data input and a data output, an output port, an input data bus that extends from the digital output of the analog-to-digital converter to the data input of the memory and an output data bus that extends from the data output of the memory to the output port. The analog-to-digital converter is structured to generate digital samples at a sampling rate. The input data bus is structured to operate at the sampling rate of the ADC. At least one of the data output of the memory, the output data bus and the output port is structured to operate at a maximum rate less than the sampling rate.
The invention also provides a method of digitally sampling an analog input signal. In the method, memory is provided, the analog input signal is digitally sampled at a sampling rate to generate digital samples and the digital samples are stored in the memory at the sampling rate. The digital samples are read out from the memory at a rate less than the sampling rate.
The invention allows the analog input signal to be sampled at a very high sampling rate without the need to output the resulting digital samples at the same high rate. Structures capable of outputting the digital samples at the rate at which the digital samples are read out from the memory can be substantially simpler and lower in cost than structures that output digital samples at the sampling rate.